Embodiments of the present invention relate to bit-error detection on a test and measurement instrument, and more particularly, to automatically searching and identifying a synchronization sub-pattern within a test pattern.
Test and measurement instruments, such as oscilloscopes, logic analyzers, or the like can be used to measure and analyze data. Test patterns can be generated and fed to a device under test (DUT). The test patterns can include signals that purposely stress the DUT. For example, the test patterns can include signal attenuation, jitter, or Spread Spectrum Clocking (SSC) to determine the operating margins of the DUT.
Bit error detection is performed by comparing the incoming bit stream with a pre-recorded correct pattern stored in memory of a test and measurement instrument. When testing is started, the test and measurement instrument waits for a synchronization sub-pattern in the input stream, and then starts comparing the incoming bits to the contents of the pre-recorded correct pattern. The synchronization sub-pattern is a unique sub-pattern in the whole repeated fixed-length test pattern.
The synchronization sub-pattern is not always known by the operator or other technical personnel involved with evaluating the DUT. It is difficult or sometimes impossible to manually identify the unique synchronization sub-pattern within the test pattern, especially if the test pattern is long or complex. One conventional approach is to repeatedly advance the selection of the candidate synchronization sub-pattern until no errors occur in the comparison of the incoming bit stream and the pre-recorded test pattern. But such approach is useful only when the incoming pattern does not contain any bit errors or pacing primitives in the signal while trying to determine the synchronization point. Moreover, such approach is resource intensive and inefficient.
Accordingly, a need remains for an improved system, method and apparatus for automatically searching for and identifying a synchronization sub-pattern within a test pattern for bit-by-bit error detection on a test and measurement instrument. Embodiments of the invention address these and other limitations in the prior art.
The foregoing and other features and advantages of the inventive concepts will become more readily apparent from the following detailed description of the example embodiments, which proceeds with reference to the accompanying drawings.